摘要 :
Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here ...
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Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes.
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This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four ...
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This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-mum CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches
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A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-/spl mu/m double-poly, double-metal (DPDM) CMOS process technology. In t...
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A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-/spl mu/m double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply.
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A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circ...
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A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circuit design techniques, and shows how an understanding of the strengths and weaknesses of these circuits influences choice of radio architecture. The CMOS approach to radio design calls for the elimination of discrete components in favor of high levels of on-chip integration which freely use translators and mix analog and digital functionality; in these respects, it departs from traditional RF circuit practices. Successful wireless devices of the future will require that radio system design evolve around these new trends in RF integration.
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The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 1...
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The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 $,times,$10.3125 Gb/s, and 10$,times,$10.3125 Gb/s for Ethernet 40 G/100 G), 8$,times$ fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification.
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Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard...
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Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%.
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The paper introduces a new approach to design a Digital Direct Frequency Synthesizer (DDFS) using a piecewise linear, minimum maximum error, polynomial approximation technique. The approach, exploiting a first order Chebyshev poly...
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The paper introduces a new approach to design a Digital Direct Frequency Synthesizer (DDFS) using a piecewise linear, minimum maximum error, polynomial approximation technique. The approach, exploiting a first order Chebyshev polynomial expansion, overcomes the performances of previously proposed DDFS based on Taylor approximation. A detailed description of the method used to compute the content of the look-up tables in the new DDFS is given, analytically showing the improved accuracy of new DDFS with respect to Taylor one. Two new Chebyshev DDFS with 80 dBc SFDR, have been designed up to the layout level, exploiting optimized arithmetic circuits. Simulation results confirm improvement in performances with respect to Taylor DDFS.
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In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, ...
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In the context of digital terrestrial TV based on the DVB-T standard, four 0.5-/spl mu/m CMOS IC's (IC1-IC4) are presented. IC1 integrates an 8-K fast Fourier transform for orthogonal frequency division multiplexing demodulation, IC2 performs channel estimation/correction, and IC3 is a forward error corrector implementing a Viterbi and a Reed-Solomon decoder. IC4, which is based on a digital signal-processing core, performs the synchronization tasks of the complete receiver. These four chips have been designed and manufactured using a 0.5-/spl mu/m, 3,3-V, triple-metal CMOS process. Their global complexity is about 500 kgates of standard cells and 1.5 Mbits of memory, which represents a total die area of 435 mm/sup 2/ in 0.5 /spl mu/m. The total power dissipation is about 3.5 W when working at nominal frequency. More generally, these four IC's constitute the digital front-end part of a global chipset receiver (specified within the European project DVBird), also including an analog front end and a MPEG2 demultiplexer IC.
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This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance ...
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This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S/sup 2/I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 /spl mu/m standard CMOS process, they demonstrate state-of-the-art performance.
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This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effec...
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This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.
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